Patents
US 9811940 B2: Bandwidth reduction using vertex shader
- Granted
- 2017-11-07
- Filed
- 2015-09-15 application 14855064
- Type
- Utility · 20 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
In graphics rendering, a texture tile is divided into a plurality of partitions, each partition having a plurality of vertices. A map indicates, for each partition, whether each partition comprises a constant color. Then the plurality of vertices are transferred to a vertex shader, which determines that at least one of the partitions comprises a constant color partition. A vertex shader applies a vertex transformation that associates a set of texel coordinates from the texture tile to each of the vertices of the constant color partition to generate a set of associated texel coordinates. A first coordinate of the set of associated texel coordinates is set to zero. A pixel shader interpolates the associated texel coordinates to generate an interpolated value and accesses a single texel in the constant color partition that corresponds to the interpolated value.
Source: PVGPATDIS, file of 2026-04-10 (ipg171107.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| QUALCOMM Innovation Center, Inc. 93 patents | US company or organization | San Diego, CA | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Shiu Wai Hui | King City, CA | 10 | PVGPATDIS, file of 2026-04-10 | |
| Yida Wang | North York, CA | 12 | PVGPATDIS, file of 2026-04-10 | |
| Stewart Chao | Markham, CA | 6 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| G06T | Image data processing or generation, in general | G06T15/04 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2016-01-19 | Assignment Assignment of assignor's interest | CHAO, STEWART signed 2015-12-04 HUI, SHIU WAI signed 2015-12-04 WANG, YIDA signed 2015-12-04 | QUALCOMM INNOVATION CENTER, INC. SAN DIEGO, CA | 37518/99 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.