Patents
US 9811388 B2: VSync aligned CPU frequency governor sampling
- Granted
- 2017-11-07
- Filed
- 2016-03-16 application 15072248
- Type
- Utility · 19 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
Systems, methods, and apparatus are herein described for reducing stuttering or skipped frames in media rendering by switching between two sampling windows of a CPU frequency governor. In particular, a sampling window for the governor can switch between a first mode and a second mode, where the first mode involves a default sampling window having a period greater than 1/f, is out of phase with or not aligned with VSync pulses, and is clocked to an internal clock of the CPU frequency governor. The second mode involves an adjusted sampling window having a period equal to 1/f, and is in phase with or aligned with VSync pulses. Further, f, can be the refresh rate of a display device. VSync pulses can be provided to the CPU frequency governor, which can use these pulses to clock the sampling window when a CPU workload becomes or is expected to become sporadic.
Source: PVGPATDIS, file of 2026-04-10 (ipg171107.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| QUALCOMM Innovation Center, Inc. 93 patents | US company or organization | San Diego, CA | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Premal Shah | San Diego, CA | 12 | PVGPATDIS, file of 2026-04-10 | |
| Rajulu Ponnada | Hyderabad, IN | 1 | PVGPATDIS, file of 2026-04-10 | |
| Omprakash Dhyade | San Diego, CA | 2 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| G06F | Electric digital data processing | G06F1/3228 | PVGPATDIS, file of 2026-04-10 |
| G06T | Image data processing or generation, in general | G06T2200/28 | PVGPATDIS, file of 2026-04-10 |
| Y02D | Climate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use | Y02D10/00 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2016-06-28 | Assignment Assignment of assignor's interest | DHYADE, OMPRAKASH signed 2016-06-15 PONNADA, RAJULU signed 2016-06-16 SHAH, PREMAL signed 2016-06-16 | QUALCOMM INNOVATION CENTER, INC. SAN DIEGO, CA | 39198/981 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.