Patents

US 9785481 B2: Power aware task scheduling on multi-processor systems

Granted
2017-10-10
Filed
2015-07-24 application 14808082
Type
Utility · 11 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

Methods and apparatus for power-based scheduling of tasks among processors are disclosed. A method may include executing processor executable code on one or more of the processors to prompt a plurality of executable tasks for scheduling among the processors. Processor-demand information is obtained about the plurality of executable tasks in addition to capacity information for each of the processors. Processor power information for each of the processors is also obtained, and the plurality of executable tasks are scheduled on the lowest power processors where processor-demands of the tasks are satisfied.

Source: PVGPATDIS, file of 2026-04-10 (ipg171010.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
QUALCOMM Innovation Center, Inc. 93 patentsUS company or organizationSan Diego, CAPVGPATDIS, file of 2026-04-10

Inventors

InventorPlacePatentsPerson pageSource
Stephen MuckleSan Diego, CA2PVGPATDIS, file of 2026-04-10
Srivatsa VaddagiriBengaluru, IN4PVGPATDIS, file of 2026-04-10
Syed Rameez MustafaSan Diego, CA2PVGPATDIS, file of 2026-04-10

CPC categories

SubclassCategoryFirst groupSource
G06FElectric digital data processingG06F9/5094PVGPATDIS, file of 2026-04-10
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy useY02D10/00PVGPATDIS, file of 2026-04-10

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

RecordedWhatFromToReel/frameSource
2016-03-24Assignment
Assignment of assignor's interest
MUCKLE, STEPHEN signed 2015-10-26
MUSTAFA, SYED RAMEEZ signed 2015-10-30
VADDAGIRI, SRIVATSA signed 2015-11-02
QUALCOMM INNOVATION CENTER, INC. SAN DIEGO, CA38243/116ECORSEXC, file of 2026-09-25

Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.

USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.