Patents

US 9696787 B2: Dynamic control of processors to reduce thermal and power costs

Granted
2017-07-04
Filed
2015-12-08 application 14962187
Type
Utility · 19 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

Systems and methods for controlling processor cores on a computing device are disclosed. One method includes tracking a load of each of a plurality of processor cores and determining a load percentage of each of the processor cores. A core is designated as a busy core if a load percentage of the core exceeds an upper threshold, and the busy core designation is removed if the load percentage of the core drops below a lower threshold. To reduce power consumption and adverse thermal effects, no more than N+M cores are maintained online wherein N is a number of busy cores and M is generally zero, but may be increased to at least one.

Source: PVGPATDIS, file of 2026-04-10 (ipg170704.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
QUALCOMM Innovation Center, Inc. 93 patentsUS company or organizationSan Diego, CAPVGPATDIS, file of 2026-04-10

Inventors

InventorPlacePatentsPerson pageSource
Saravana Krishnan KannanSan Diego, CA6PVGPATDIS, file of 2026-04-10
Junjie WuSan Diego, CA13PVGPATDIS, file of 2026-04-10

CPC categories

SubclassCategoryFirst groupSource
G06FElectric digital data processingG06F1/3234PVGPATDIS, file of 2026-04-10
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy useY02D10/00PVGPATDIS, file of 2026-04-10

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

RecordedWhatFromToReel/frameSource
2016-02-19Assignment
Assignment of assignor's interest
KANNAN, SARAVANA KRISHNAN signed 2016-02-09
WU, JUNJIE signed 2016-02-12
QUALCOMM INNOVATION CENTER, INC. SAN DIEGO, CA37773/885ECORSEXC, file of 2026-09-25

Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.

USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.