Patents
US 9691628 B2: Process for silicon nitride removal selective to SiGex
- Granted
- 2017-06-27
- Filed
- 2015-09-23 application 14863126
- Type
- Utility · 17 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
A method for selectively removing silicon nitride is described. In particular, the method includes providing a substrate having a surface with silicon nitride exposed on at least one portion of the surface and SiGex (x is greater than or equal to zero) exposed on at least another portion of the surface, and dispensing an oxidizing agent onto the surface of the substrate to oxidize the exposed SiGex. Thereafter, the method includes dispensing a silicon nitride etching agent as a liquid stream onto the surface of the substrate to remove at least a portion of the silicon nitride.
Source: PVGPATDIS, file of 2026-04-10 (ipg170627.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| TEL FSI, INC. 34 patents | US company or organization | Chaska, MN | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Jeffery W. Butterbaugh | Eden Prairie, MN | 14 | PVGPATDIS, file of 2026-04-10 | |
| Anthony S. Ratkovich | Bloomington, MN | 3 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| H01L | Semiconductor devices not covered by class h10 | H01L21/31111 | PVGPATDIS, file of 2026-04-10 |
| H10P | Generic processes or apparatus for the manufacture or treatment of devices covered by class h10 | H10P50/283 | PVGPATDIS, file of 2026-04-10 |
| B81C | Processes or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems | B81C1/00539 | PVGPATDIS, file of 2026-04-10 |
| H10D | Inorganic electric semiconductor devices | H10D30/0275 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2020-07-30 | Correction Conversion | TEL FSI, INC. signed 2019-12-31 | TEL MANUFACTURING AND ENGINEERING OF AMERICA, INC. CHASKA, MN | 53366/139 | PASDL, file of 2026-10-15 |
| 2015-09-28 | Assignment Assignment of assignor's interest | BUTTERBAUGH, JEFFERY W. signed 2015-09-25 RATKOVICH, ANTHONY S. signed 2015-09-25 | TEL FSI, INC. CHASKA, MN | 36670/948 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.