Patents
US 9690551 B2: Auto-vectorization in just-in-time compilers for dynamically typed programming languages
- Granted
- 2017-06-27
- Filed
- 2016-03-28 application 15083157
- Type
- Utility · 8 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
A computing device with an optimizing compiler is disclosed that is configured to generate optimized machine code including a vector operation corresponding to multiple scalar operations where the vector operation is a single operation on multiple pairs of operands. The optimizing compiler includes a vector guard condition generator configured to generate a vector guard condition for one or more vector operations, a mapping module to generate a mapping between elements of the vector guard condition and positions of the relevant scalar operations in the non-optimized machine code or intermediate representation of the source code, and a guard condition handler configured to initiate execution from a particular scalar operation in the non-optimized machine code or intermediate representation if the vector guard condition is triggered. The computing device may include a non-optimizing compiler and/or an interpreter to perform execution of the scalar operations if the vector guard condition is triggered.
Source: PVGPATDIS, file of 2026-04-10 (ipg170627.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| QUALCOMM Innovation Center, Inc. 93 patents | US company or organization | San Diego, CA | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Subrato Kumar De | San Diego, CA | 29 | PVGPATDIS, file of 2026-04-10 | |
| Zaheer Ahmad | San Diego, CA | 3 | PVGPATDIS, file of 2026-04-10 | |
| Dineel D. Sule | San Diego, CA | 11 | PVGPATDIS, file of 2026-04-10 | |
| Yang Ding | San Diego, CA | 59 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| G06F | Electric digital data processing | G06F8/41 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2016-06-28 | Assignment Assignment of assignor's interest | AHMAD, ZAHEER signed 2016-06-23 DE, SUBRATO K. signed 2016-06-23 DING, YANG signed 2016-06-23 SULE, DINEEL D. signed 2016-06-23 | QUALCOMM INNOVATION CENTER, INC. SAN DIEGO, CA | 39032/951 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.