Patents

US 9506973 B2: High voltage chuck for a probe station

Granted
2016-11-29
Filed
2011-04-11 application 13702054
Type
Utility · 12 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under test. An upper insulating layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper conductive layer, and a lower surface. A middle conductive layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper insulating layer, and a lower surface.

Source: PVGPATDIS, file of 2026-04-10 (ipg161129.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
Cascade Microtech, Inc. 96 patentsUS company or organizationBeaverton, ORCASCADE MICROTECH INC SEC filer EXACT medium confidence: identical full name, one of each nationallyPVGPATDIS, file of 2026-04-10

Inventors

InventorPlacePatentsPerson pageSource
Michael E. SimmonsColton, OR13PVGPATDIS, file of 2026-04-10
Kazuki NegishiBeaverton, OR18PVGPATDIS, file of 2026-04-10
Roy JensenJacksonville, OR3PVGPATDIS, file of 2026-04-10
Ryan GarrisonBeaverton, OR4PVGPATDIS, file of 2026-04-10
Philip WolfBeaverton, OR10PVGPATDIS, file of 2026-04-10

CPC categories

SubclassCategoryFirst groupSource
H01LSemiconductor devices not covered by class h10H01L21/6838PVGPATDIS, file of 2026-04-10
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h10H10P72/78PVGPATDIS, file of 2026-04-10
G01RMeasuring electric variables; measuring magnetic variablesG01R31/2601PVGPATDIS, file of 2026-04-10
Y10TTechnical subjects covered by former us classificationY10T279/11PVGPATDIS, file of 2026-04-10

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

RecordedWhatFromToReel/frameSource
2025-08-07Release of security interest
Release of security interest
HSBC BANK USA, NATIONAL ASSOCIATION signed 2025-08-06FORMFACTOR, INC. LIVERMORE, CA72853/1PASDL, file of 2026-10-15
2021-09-01Assignment
Assignment of assignor's interest
FORMFACTOR BEAVERTON, INC. signed 2021-08-26FORMFACTOR, INC. LIVERMORE, CA57393/609PASDL, file of 2026-10-15
2018-07-18Name change
Change of name
CASCADE MICROTECH, INC. signed 2018-05-14FORMFACTOR BEAVERTON, INC. BEAVERTON, OR46573/664PASDL, file of 2026-10-15
2016-07-12Security interest Security interest
Security interest in united states patents and trademarks
FORMFACTOR, INC. signed 2016-06-24
ASTRIA SEMICONDUCTOR HOLDINGS, INC. signed 2016-06-24
CASCADE MICROTECH, INC. signed 2016-06-24
MICRO-PROBE INCORPORATED signed 2016-06-24
HSBC BANK USA, NATIONAL ASSOCIATION SAN FRANCISCO, CA39184/280PASDL, file of 2026-10-15
2012-12-04Assignment
Assignment of assignor's interest
GARRISON, RYAN signed 2012-11-14
NEGISHI, KAZUKI signed 2012-11-14
SIMMONS, MICHAEL E. signed 2012-11-14
WOLF, PHILIP signed 2012-11-14
JENSEN, ROY signed 2012-11-28
CASCADE MICROTECH, INC. BEAVERTON, OR29403/986ECORSEXC, file of 2026-09-25

Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.

USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.