Patents
US 9412639 B2: Method of using separate wafer contacts during wafer processing
- Granted
- 2016-08-09
- Filed
- 2014-12-05 application 14562386
- Type
- Utility · 7 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
Embodiments of the invention are directed towards improving on-wafer process performance and processing at increased processing fluid/wafer temperature while maintaining good process performance. A method for processing a wafer in a process chamber is described where the process chamber includes a wafer holder having first and second sets of edge grippers for independently securing the wafer at the wafer edge during processing, treating the wafer with a first processing fluid while securing the wafer with the first set of edge grippers, but not with the second set of edge grippers, treating the wafer with a second processing fluid while securing the wafer with the first set of edge grippers, but not with the second set of edge grippers, and treating the wafer with a third processing fluid while securing the wafer with the second set of edge grippers, but not with the first set of edge grippers.
Source: PVGPATDIS, file of 2026-04-10 (ipg160809.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| TEL FSI, INC. 34 patents | US company or organization | Chaska, MN | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Kevin L. Siefering | Excelsior, MN | 8 | PVGPATDIS, file of 2026-04-10 | |
| David DeKraker | Burnsville, MN | 14 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| H01L | Semiconductor devices not covered by class h10 | H01L21/68728 | PVGPATDIS, file of 2026-04-10 |
| H10P | Generic processes or apparatus for the manufacture or treatment of devices covered by class h10 | H10P72/7608 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2020-07-30 | Correction Conversion | TEL FSI, INC. signed 2019-12-31 | TEL MANUFACTURING AND ENGINEERING OF AMERICA, INC. CHASKA, MN | 53366/139 | PASDL, file of 2026-10-15 |
| 2015-01-07 | Assignment Assignment of assignor's interest | SIEFERING, KEVIN L. signed 2014-12-05 DEKRAKER, DAVID signed 2014-12-08 | TEL FSI, INC. CHASKA, MN | 34655/673 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.