Patents
US 9374540 B1: Multi-register bank enhanced digital time delay integration using CMOS ROIC
- Granted
- 2016-06-21
- Filed
- 2015-01-13 application 14595419
- Type
- Utility · 20 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
An integrated circuit includes an array of pixels for capturing and processing successive image frames of a moving scene, the array including at least one row of pixels (inputs); and at least one current value register, in which the current value register is configured to store current pixel values captured from the array (inputs). Also included is at least one set of multiple accumulated value registers, in which each accumulated value register is configured to communicate with the current value register. Furthermore, there is included at least one readout register, in which the readout register is configured to communicate with the set of accumulated value registers. A controller is also included for shifting and summing the rows of pixels and outputting a summed column as a time delayed integrated (TDI) signal.
Source: PVGPATDIS, file of 2026-04-10 (ipg160621.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| Exelis Inc. 229 patents | US company or organization | Herndon, VA | EXELIS INC. State business registration EXACT high confidence: identical full name and state EXELIS INC. SEC filer EXACT medium confidence: identical full name, one of each nationally | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Andrew P. Sacco | Pittsford, NY | 5 | PVGPATDIS, file of 2026-04-10 | |
| J. Daniel Newman | Pittsford, NY | 1 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| H04N | Pictorial communication, e.g. television | H04N25/711 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2017-12-04 | Merger Merger | EXELIS INC. signed 2015-12-23 | HARRIS CORPORATION MELBOURNE, FL | 44284/675 | ECORSEXC, file of 2026-09-25 |
| 2015-01-13 | Assignment Assignment of assignor's interest | NEWMAN, J. DANIEL signed 2015-01-09 SACCO, ANDREW P. signed 2015-01-09 | EXELIS, INC. MCLEAN, VA | 34695/997 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.