Patents

US 9207708 B2: Abnormal clock rate detection in imaging sensor arrays

Granted
2015-12-08
Filed
2013-12-13 application 14106666
Type
Utility · 24 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select the current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.

Source: PVGPATDIS, file of 2026-04-10 (ipg151208.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
FLIR Systems, Inc. 370 patentsUS company or organizationWilsonville, ORFLIR SYSTEMS INC Form D issuer EXACT high confidence: identical full name and state
FLIR SYSTEMS INC SEC filer EXACT medium confidence: identical full name, one of each nationally
PVGPATDIS, file of 2026-04-10

Inventors

InventorPlacePatentsPerson pageSource
Brian B. SimolonLompoc, CA22PVGPATDIS, file of 2026-04-10
Eric A. KurthLompoc, CA59PVGPATDIS, file of 2026-04-10
Jim GoodlandLompoc, CA4PVGPATDIS, file of 2026-04-10
Mark NussmeierGoleta, CA30PVGPATDIS, file of 2026-04-10
Nicholas HögastenLompoc, CA92PVGPATDIS, file of 2026-04-10
Theodore R. HoelterGoleta, CA74PVGPATDIS, file of 2026-04-10
Katrin StrandemarRimbo, SE77PVGPATDIS, file of 2026-04-10
Pierre BoulangerGoleta, CA60PVGPATDIS, file of 2026-04-10
Barbara SharpLompoc, CA45PVGPATDIS, file of 2026-04-10

CPC categories

SubclassCategoryFirst groupSource
G06FElectric digital data processingG06F1/14PVGPATDIS, file of 2026-04-10
G01RMeasuring electric variables; measuring magnetic variablesG01R23/00PVGPATDIS, file of 2026-04-10
H04NPictorial communication, e.g. televisionH04N23/20PVGPATDIS, file of 2026-04-10

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

RecordedWhatFromToReel/frameSource
2021-11-24Merger
Merger and change of name
FIREWORK MERGER SUB II, LLC signed 2021-05-14
FLIR SYSTEMS, INC. signed 2021-05-14
TELEDYNE FLIR, LLC THOUSAND OAKS, CA58832/915ECORSEXC, file of 2026-09-25
2014-01-30Assignment
Assignment of assignor's interest
KURTH, ERIC A. signed 2013-12-20
HOGASTEN, NICHOLAS signed 2014-01-09
STRANDEMAR, KATRIN signed 2014-01-09
SIMOLON, BRIAN signed 2014-01-10
HOELTER, THEODORE R. signed 2014-01-13
SHARP, BARBARA signed 2014-01-15
BOULANGER, PIERRE signed 2014-01-16
NUSSMEIER, MARK signed 2014-01-24
GOODLAND, JIM signed 2014-01-30
FLIR SYSTEMS, INC. WILSONVILLE, OR32099/175ECORSEXC, file of 2026-09-25

Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.

USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.