Patents

US 8725950 B2: Horizontally-shared cache victims in multiple core processors

Granted
2014-05-13
Filed
2010-06-30 application 12828056
Type
Utility · 15 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

A processor includes multiple processor core units, each including a processor core and a cache memory. Victim lines evicted from a first processor core unit's cache may be stored in another processor core unit's cache, rather than written back to system memory. If the victim line is later requested by the first processor core unit, the victim line is retrieved from the other processor core unit's cache. The processor has low latency data transfers between processor core units. The processor transfers victim lines directly between processor core units' caches or utilizes a victim cache to temporarily store victim lines while searching for their destinations. The processor evaluates cache priority rules to determine whether victim lines are discarded, written back to system memory, or stored in other processor core units' caches. Cache priority rules can be based on cache coherency data, load balancing schemes, and architectural characteristics of the processor.

Source: PVGPATDIS, file of 2026-04-10 (ipg140513.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
MIPS Technologies, Inc. 81 patentsUS company or organizationMountain View, CAMIPS TECHNOLOGIES, INC. State business registration EXACT high confidence: identical full name and state
MIPS TECHNOLOGIES INC SEC filer EXACT medium confidence: identical full name, one of each nationally
PVGPATDIS, file of 2026-04-10

Inventors

InventorPlacePatentsPerson pageSource
Sanjay VishinSunnyvale, CA11PVGPATDIS, file of 2026-04-10

CPC categories

SubclassCategoryFirst groupSource
G06FElectric digital data processingG06F12/0806PVGPATDIS, file of 2026-04-10
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy useY02D10/00PVGPATDIS, file of 2026-04-10

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

RecordedWhatFromToReel/frameSource
2022-12-29Release of security interest
Release of security interest
CAPITAL FINANCE ADMINISTRATION, LLC, AS ADMINISTRATIVE AGENT signed 2022-12-29MIPS TECH, LLC SAN JOSE, CA
WAVE COMPUTING INC. SAN JOSE, CA
62251/251PASDL, file of 2026-10-15
2021-06-14Release of security interest
Release of security interest
WAVE COMPUTING LIQUIDATING TRUST signed 2021-06-11MIPS TECH, INC. SAN JOSE, CA
HELLOSOFT, INC. SAN JOSE, CA
WAVE COMPUTING (UK) LIMITED SAN JOSE, CA
IMAGINATION TECHNOLOGIES, INC. SAN JOSE, CA
CAUSTIC GRAPHICS, INC. SAN JOSE, CA
MIPS TECH, LLC SAN JOSE, CA
WAVE COMPUTING, INC. SAN JOSE, CA
56589/606PASDL, file of 2026-10-15
2021-06-14Security interest Security interest
Security interest
MIPS TECH, LLC signed 2021-06-11
WAVE COMPUTING, INC. signed 2021-06-11
CAPITAL FINANCE ADMINISTRATION, LLC CHICAGO, IL56558/903PASDL, file of 2026-10-15
2021-02-26Security interest Security interest
Security interest
WAVE COMPUTING, INC. signed 2021-02-26
MIPS TECH, LLC signed 2021-02-26
MIPS TECH, INC. signed 2021-02-26
HELLOSOFT, INC. signed 2021-02-26
WAVE COMPUTING (UK) LIMITED signed 2021-02-26
IMAGINATION TECHNOLOGIES, INC. signed 2021-02-26
CAUSTIC GRAPHICS, INC. signed 2021-02-26
WAVE COMPUTING LIQUIDATING TRUST PACIFIC PALISADES, CA55429/532PASDL, file of 2026-10-15
2018-08-09Name change
Change of name
MIPS TECH LIMITED signed 2017-11-07MIPS TECH, LLC SANTA CLARA, CA46752/698ECORSEXC, file of 2026-09-25
2018-04-11Name change
Change of name
IMAGINATION TECHNOLOGIES, LLC signed 2017-11-07MIPS TECH, LLC SANTA CLARA, CA45927/625ECORSEXC, file of 2026-09-25
2017-04-20Name change
Change of name
MIPS TECHNOLOGIES, INC. signed 2014-03-10IMAGINATION TECHNOLOGIES, LLC SANTA CLARA, CA42301/84ECORSEXC, file of 2026-09-25

Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.

USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.