Patents
US 8392663 B2: Coherent instruction cache utilizing cache-op execution resources
- Granted
- 2013-03-05
- Filed
- 2008-12-10 application 12332291
- Type
- Utility · 20 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
A multiprocessor system maintains cache coherence among processors in a coherent domain. Within the coherent domain, a first processor can receive a command to perform a cache maintenance operation. The first processor can determine whether the cache maintenance operation is a coherent operation. For coherent operations, the first processor sends a coherent request message for distribution to other processors in the coherent domain and can cancel execution of the cache maintenance operation pending receipt of intervention messages corresponding to the coherent request. The intervention messages can reflect a global ordering of coherence traffic in the multiprocessor system and can include instructions for maintaining a data cache and an instruction cache of the first processor. Cache maintenance operations that are determined to be non-coherent can be executed at the first processor without sending the coherent request.
Source: PVGPATDIS, file of 2026-04-10 (ipg130305.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| MIPS Technologies, Inc. 81 patents | US company or organization | Sunnyvale, CA | MIPS TECHNOLOGIES, INC. State business registration EXACT high confidence: identical full name and state MIPS TECHNOLOGIES INC SEC filer EXACT medium confidence: identical full name, one of each nationally | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Ryan C. Kinter | Seattle, WA | 9 | PVGPATDIS, file of 2026-04-10 | |
| Darren M. Jones | Los Altos, CA | 5 | PVGPATDIS, file of 2026-04-10 | |
| Matthias Knoth | San Jose, CA | 13 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| G06F | Electric digital data processing | G06F9/3834 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2014-06-02 | Assignment Assignment of assignor's interest | BRIDGE CROSSING, LLC signed 2014-01-31 | ARM FINANCE OVERSEAS LIMITED CAMBRIDGE | 33074/58 | ECORSEXC, file of 2026-09-25 |
| 2013-04-12 | Assignment Assignment of assignor's interest | MIPS TECHNOLOGIES, INC. signed 2013-02-06 | BRIDGE CROSSING, LLC LAMBERTVILLE, NJ | 30202/440 | ECORSEXC, file of 2026-09-25 |
| 2008-12-12 | Assignment Assignment of assignor's interest | KINTER, RYAN C. signed 2008-12-08 JONES, DARREN M. signed 2008-12-10 KNOTH, MATTHIAS signed 2008-12-10 | MIPS TECHNOLOGIES, INC. MOUNTAIN VIEW, CA | 21978/177 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.