Patents
US 8392651 B2: Data cache way prediction
- Granted
- 2013-03-05
- Filed
- 2008-08-20 application 12194936
- Type
- Utility · 24 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
A microprocessor includes one or more N-way caches and a way prediction logic that selectively enables and disables the cache ways so as to reduce the power consumption. The way prediction logic receives an address and predicts in which one of the cache ways the data associated with the address is likely to be stored. The way prediction logic causes an enabling signal to be supplied only to the way predicted to contain the requested data. The remaining (N−1) of the cache ways do not receive the enabling signal. The power consumed by the cache is thus significantly reduced.
Source: PVGPATDIS, file of 2026-04-10 (ipg130305.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| MIPS Technologies, Inc. 81 patents | US company or organization | Sunnyvale, CA | MIPS TECHNOLOGIES, INC. State business registration EXACT high confidence: identical full name and state MIPS TECHNOLOGIES INC SEC filer EXACT medium confidence: identical full name, one of each nationally | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Ajit Mylavarapu | Mountain View, CA | 26 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| G06F | Electric digital data processing | G06F1/3203 | PVGPATDIS, file of 2026-04-10 |
| Y02D | Climate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use | Y02D10/00 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2014-06-02 | Assignment Assignment of assignor's interest | BRIDGE CROSSING, LLC signed 2014-01-31 | ARM FINANCE OVERSEAS LIMITED CAMBRIDGE | 33074/58 | ECORSEXC, file of 2026-09-25 |
| 2013-04-12 | Assignment Assignment of assignor's interest | MIPS TECHNOLOGIES, INC. signed 2013-02-06 | BRIDGE CROSSING, LLC LAMBERTVILLE, NJ | 30202/440 | ECORSEXC, file of 2026-09-25 |
| 2008-08-20 | Assignment Assignment of assignor's interest | MYLAVARAPU, AJIT KARTHIK signed 2008-08-19 | MIPS TECHNOLOGIES, INC. MOUNTAIN VIEW, CA | 21418/211 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.