Patents
US 12772821 B2: Memory cell structures using full backside connectivity
- Granted
- 2026-10-20
- Filed
- 2023-09-18 application 18469501
- Type
- Utility · 18 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
In an aspect, a semiconductor memory cell comprises gate structures separated by source or drain (S/D) structures, a frontside (FS) inter-layer dielectric (FS-ILD) layer above the gate and S/D structures, FS metal zero (FM0) interconnects above the FS-ILD layer, a backside (BS) inter-layer dielectric (BS-ILD) layer below the gate and S/D structures, BS metal zero (BM0) interconnects below the BS-ILD layer, at least one FS S/D contact (FSDC) electrically connecting an FM0 interconnect to a top surface of an S/D structure, and at least one BS S/D contact (BSDC) electrically connecting a BM0 interconnect to a bottom surface of an S/D structure. The semiconductor memory cell comprises NFETs and PFETs to form a cross-coupled inverter pair. For each inverter in the pair, one of VDD and VSS are provided by an FSDC and the other of VDD and VSS is provided by a BSDC.
Source: PTBLXML, file of 2026-10-20 (ipgb20261020.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| Qualcomm Incorporated 40,593 patents | US company or organization | San Diego, CA | PTBLXML, file of 2026-10-20 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Shreesh Narasimha | Charlotte, NC | PTBLXML, file of 2026-10-20 | ||
| Yan Sun | San Diego, CA | PTBLXML, file of 2026-10-20 | ||
| Yandong Gao | San Diego, CA | 9 | PTBLXML, file of 2026-10-20 | |
| Peijie Feng | San Diego, CA | 21 | PTBLXML, file of 2026-10-20 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| H10W | Generic packages, interconnections, connectors or other constructional details of devices covered by class h10 | H10W20/20 | PTBLXML, file of 2026-10-20 |
| H10B | Electronic memory devices | H10B10/125 | PTBLXML, file of 2026-10-20 |
| H10D | Inorganic electric semiconductor devices | H10D30/6729 | PTBLXML, file of 2026-10-20 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
No recorded assignments or security interests on file for this patent.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.