Patents

US 12772796 B2: Semiconductor device fabrication method using a deposition apparatus with a contoured wafer carrier ring

Granted
2026-10-20
Filed
2023-09-13 application 18466108
Type
Utility · 5 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

A method includes placing a wafer on a step of a carrier ring in a first vacuum enclosure such that a backside surface of the wafer contacts the step, depositing a film on an exposed portion of the backside surface of the wafer while the backside surface of the wafer is in contact with the step, and depositing a semiconductor device on a front side of the wafer which is opposite to the backside surface of the wafer. The carrier ring includes a bottom surface surrounding an opening in the carrier ring, an upper top surface, a lower top surface of the step, and an inner surface which connects the upper top surface and the lower top surface, and which is inclined outward at a non-zero taper angle relative to the vertical direction which perpendicular to the lower top surface of the step.

Source: PTBLXML, file of 2026-10-20 (ipgb20261020.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
Sandisk Technologies, Inc. 4,933 patentsUS company or organizationMilpitas, CASANDISK TECHNOLOGIES LLC State business registration FUZZY medium confidence: same name (legal endings aside) and statePTBLXML, file of 2026-10-20

Inventors

InventorPlacePatentsPerson pageSource
Makoto TsutsueYokkaichi, JP18PTBLXML, file of 2026-10-20

CPC categories

SubclassCategoryFirst groupSource
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h10H10P72/7611PTBLXML, file of 2026-10-20
C23CCoating metallic material; coating material with metallic material; surface treatment of metallic material by diffusion into the surface, by chemical conversion or substitution; coating by vacuum evaporation, by sputtering, by ion implantation or by chemical vapour deposition, in generalC23C16/4585PTBLXML, file of 2026-10-20

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

RecordedWhatFromToReel/frameSource
2025-04-25Release of security interest
Partial release of security interests
JPMORGAN CHASE BANK, N.A., AS AGENT signed 2025-04-24SANDISK TECHNOLOGIES, INC. MILPITAS, CA71382/1PASDL, file of 2026-10-15

Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.

USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.