Patents

US 12772464 B2: Packaged memory device with overhang support structure

Granted
2026-10-20
Filed
2023-08-11 application 18448296
Type
Utility · 20 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

A memory device includes a substrate, a controller die attached to the substrate, and a memory die stack. The memory die stack includes a first silicon die having a first contact pad surface and a bottom surface attached to the substrate. The memory die stack includes a second silicon die stacked on the first silicon die, the second silicon die including a second contact pad surface. An overhang portion of the second silicon die extends beyond the first silicon die. The memory die stack includes a printed support structure attached to the substrate, the printed support structure supporting the overhang portion of the second silicon die, and one or more bond wires that electrically connect the first and second contact pad surfaces to the substrate, thereby electrically connecting the first and second silicon dies to the controller die by way of the substrate.

Source: PTBLXML, file of 2026-10-20 (ipgb20261020.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
Sandisk Technologies, Inc. 4,933 patentsUS company or organizationMilpitas, CASANDISK TECHNOLOGIES LLC State business registration FUZZY medium confidence: same name (legal endings aside) and statePTBLXML, file of 2026-10-20

Inventors

InventorPlacePatentsPerson pageSource
Shujun ZhengShanghai, CNPTBLXML, file of 2026-10-20
Jason XiaoShanghai, CNPTBLXML, file of 2026-10-20
Youhua XuShanghai, CNPTBLXML, file of 2026-10-20
Yvonne MingShanghai, CNPTBLXML, file of 2026-10-20
Jiun Dong LoehPenang, MYPTBLXML, file of 2026-10-20
Shino JianShanghai, CNPTBLXML, file of 2026-10-20
Fen YuShanghai, CN11PTBLXML, file of 2026-10-20

CPC categories

SubclassCategoryFirst groupSource
H10BElectronic memory devicesH10B80/00PTBLXML, file of 2026-10-20
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h10H10W90/00PTBLXML, file of 2026-10-20

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

RecordedWhatFromToReel/frameSource
2025-04-25Release of security interest
Partial release of security interests
JPMORGAN CHASE BANK, N.A., AS AGENT signed 2025-04-24SANDISK TECHNOLOGIES, INC. MILPITAS, CA71382/1PASDL, file of 2026-10-15

Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.

USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.