Patents
US 12772451 B2: Stairless three-dimensional memory device and method of making thereof by forming replacement word lines through memory openings
- Granted
- 2026-10-20
- Filed
- 2023-07-14 application 18352752
- Type
- Utility · 5 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.
Source: PTBLXML, file of 2026-10-20 (ipgb20261020.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| Sandisk Technologies, Inc. 4,933 patents | US company or organization | Milpitas, CA | SANDISK TECHNOLOGIES LLC State business registration FUZZY medium confidence: same name (legal endings aside) and state | PTBLXML, file of 2026-10-20 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Naohiro Hosoda | Yokkaichi, JP | 24 | PTBLXML, file of 2026-10-20 | |
| Kazuki Isozumi | Yokkaichi, JP | 8 | PTBLXML, file of 2026-10-20 | |
| Takayuki Maekura | Yokkaichi, JP | 7 | PTBLXML, file of 2026-10-20 | |
| Hiroyuki Ogawa | Nagoya, JP | 182 | PTBLXML, file of 2026-10-20 | |
| Koichi Matsuno | Fremont, CA | 53 | PTBLXML, file of 2026-10-20 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| H10B | Electronic memory devices | H10B43/27 | PTBLXML, file of 2026-10-20 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2025-04-25 | Release of security interest Partial release of security interests | JPMORGAN CHASE BANK, N.A., AS AGENT signed 2025-04-24 | SANDISK TECHNOLOGIES, INC. MILPITAS, CA | 71382/1 | PASDL, file of 2026-10-15 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.