Patents

US 12772440 B2: Method and structure of low-k spacer using post-treatment for memory applications

Granted
2026-10-20
Filed
2024-05-13 application 18662620
Type
Utility · 20 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

Exemplary methods of manufacturing 2D DRAM and 3D DRAM devices include etching a portion of a low-k spacer material from a substrate. The methods may include exposing the remaining portion of the low-k spacer material of a 2D DRAM bit line to a carbon-containing precursor, to replenish the carbon content in the low-k spacer material. Additional methods may include exposing the remaining portion of the low-k spacer material of a 3D DRAM word line to a carbon-containing precursor to replenish the carbon content in the low-k spacer material. Further embodiments may include simultaneous treatment with ultraviolet (UV) radiation.

Source: PTBLXML, file of 2026-10-20 (ipgb20261020.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
Applied Materials, Inc. 9,683 patentsUS company or organizationSanta Clara, CAPTBLXML, file of 2026-10-20

Inventors

InventorPlacePatentsPerson pageSource
Chang Seok KangSanta Clara, CA68PTBLXML, file of 2026-10-20
Raghuveer Satya MakalaCampbell, CAPTBLXML, file of 2026-10-20
Fredrick FishburnBelmont, CA25PTBLXML, file of 2026-10-20
Hsueh Chung ChenCohoes, NYPTBLXML, file of 2026-10-20
Balasubramanian PranatharthiharanSan Jose, CA229PTBLXML, file of 2026-10-20

CPC categories

SubclassCategoryFirst groupSource
H10BElectronic memory devicesH10B12/482PTBLXML, file of 2026-10-20

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

No recorded assignments or security interests on file for this patent.

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