Patents

US 12772433 B2: Single gate three-dimensional (3D) dynamic random-access memory (DRAM) devices

Granted
2026-10-20
Filed
2023-08-22 application 18236922
Type
Utility · 20 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

A memory cell array includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including an active region, a cell transistor having a single gate above the active region in the first direction, and a cell capacitor having a bottom electrode layer that is electrically connected to the active region.

Source: PTBLXML, file of 2026-10-20 (ipgb20261020.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
Applied Materials, Inc. 9,683 patentsUS company or organizationSanta Clara, CAPTBLXML, file of 2026-10-20

Inventors

InventorPlacePatentsPerson pageSource
Chang Seok KangSan Jose, CA68PTBLXML, file of 2026-10-20
Sung-Kwan KangSan Jose, CA35PTBLXML, file of 2026-10-20

CPC categories

SubclassCategoryFirst groupSource
H10BElectronic memory devicesH10B12/30PTBLXML, file of 2026-10-20

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

No recorded assignments or security interests on file for this patent.

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