Patents
US 12770699 B2: Non-volatile memory with smart tail detection read mode without erase time penalty
- Granted
- 2026-10-20
- Filed
- 2024-12-27 application 19003033
- Type
- Utility · 20 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
To determine NAND memory blocks with an upper tail or a lower tail of select gate threshold voltage levels, a tail detection read is introduced into the erase process. To minimize the time penalty on the erase process, the tail detection read is only performed for a specified loop in the erase verify process. More specifically, in an erase process using an algorithm of a loop of applying an erase pulse followed by an erase verify operation, an erase loop count is maintained and incremented at each loop. If the block fails erase verify, before looping back for the next erase pulse a tail detection read is performed, but only if the erase loop count equals a specified value (which can be a settable parameter); otherwise, the tail detection read is not performed.
Source: PTBLXML, file of 2026-10-20 (ipgb20261020.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| Sandisk Technologies, Inc. 4,933 patents | US company or organization | Milpitas, CA | SANDISK TECHNOLOGIES LLC State business registration FUZZY medium confidence: same name (legal endings aside) and state | PTBLXML, file of 2026-10-20 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Jojo Xing | Shanghai, CN | 4 | PTBLXML, file of 2026-10-20 | |
| Xuan Tian | Shanghai, CN | 26 | PTBLXML, file of 2026-10-20 | |
| Liang Li | Shanghai, CN | PTBLXML, file of 2026-10-20 | ||
| Vincent Yin | Shanghai, CN | 12 | PTBLXML, file of 2026-10-20 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| G11C | Static stores | G11C16/3472 | PTBLXML, file of 2026-10-20 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2025-04-25 | Release of security interest Partial release of security interests | JPMORGAN CHASE BANK, N.A., AS AGENT signed 2025-04-24 | SANDISK TECHNOLOGIES, INC. MILPITAS, CA | 71382/1 | PASDL, file of 2026-10-15 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.