Patents
US 12764960 B2: Three-dimensional semiconductor device containing core-bias electrode surrounded by vertical semiconductor channel and method of forming the same
- Granted
- 2026-10-13
- Filed
- 2024-05-10 application 18660791
- Type
- Utility · 20 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
A semiconductor device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel that is laterally surrounded by the memory film, a drain region contacting a first end portion of the vertical semiconductor channel, a dielectric core surrounded by the vertical semiconductor channel, and a core-bias electrode surrounded by the dielectric core. A source layer contacts a second end portion of the vertical semiconductor channel and an end portion of the core-bias electrode.
Source: PTBLXML, file of 2026-10-13 (ipgb20261013.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| Sandisk Technologies, Inc. 4,933 patents | US company or organization | Milpitas, CA | SANDISK TECHNOLOGIES LLC State business registration FUZZY medium confidence: same name (legal endings aside) and state | PTBLXML, file of 2026-10-13 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Wei Cao | Fremont, CA | 86 | PTBLXML, file of 2026-10-13 | |
| Zhixin Cui | Nagoya, JP | 51 | PTBLXML, file of 2026-10-13 | |
| Koichi Matsuno | Fremont, CA | 53 | PTBLXML, file of 2026-10-13 | |
| Xiang Yang | Santa Clara, CA | 265 | PTBLXML, file of 2026-10-13 | |
| Masaaki Higashitani | Cupertino, CA | 220 | PTBLXML, file of 2026-10-13 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| H10B | Electronic memory devices | H10B43/27 | PTBLXML, file of 2026-10-13 |
| G11C | Static stores | G11C16/0483 | PTBLXML, file of 2026-10-13 |
| H10W | Generic packages, interconnections, connectors or other constructional details of devices covered by class h10 | H10W20/435 | PTBLXML, file of 2026-10-13 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2025-04-25 | Release of security interest Partial release of security interests | JPMORGAN CHASE BANK, N.A., AS AGENT signed 2025-04-24 | SANDISK TECHNOLOGIES, INC. MILPITAS, CA | 71382/1 | PASDL, file of 2026-10-15 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.