Patents
US 12665613 B2: Self-clocking signal protocol
- Granted
- 2026-06-23
- Filed
- 2024-05-13 application 18662044
- Type
- Utility · 25 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
A signal encoding and decoding protocol to transmit both clock information and a data payload in a single line is disclosed. Data may be encoded in a unipolar non-return-to-zero line in which an initial pulse width determines a clock frequency, followed by a series of pulses indicating the data payload. Each clock transition following an initial synchronization pulse indicates a data bit in which the value of the bit is determined in relation to the previous bit. Edge information may indicate a change in bit value from the previous bit. If the transmission signal remains at the same level for a subsequent clock period, the bit value remains the same.
Source: PTBLXML, file of 2026-06-23 (ipgb20260623.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| Allegro MicroSystems, LLC 910 patents | US company or organization | Manchester, NH | ALLEGRO MICROSYSTEMS, INC. SEC filer FUZZY low confidence: same name (legal endings aside), one of each nationally | PTBLXML, file of 2026-06-23 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Ahmad Nour Halawani | Heidelberg, DE | 5 | PTBLXML, file of 2026-06-23 | |
| Emil Pavlov | Heidelberg, DE | 11 | PTBLXML, file of 2026-06-23 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| H03M | Coding; decoding; code conversion in general | H03M7/6011 | PTBLXML, file of 2026-06-23 |
| G06F | Electric digital data processing | G06F1/08 | PTBLXML, file of 2026-06-23 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2024-05-14 | Assignment Assignment of assignor's interest | HALAWANI, AHMAD NOUR signed 2024-05-11 PAVLOV, EMIL signed 2024-05-13 ALLEGRO MICROSYSTEMS GERMANY GMBH signed 2024-05-13 ALLEGRO MICROSYSTEMS EUROPE LIMITED signed 2024-05-13 | ALLEGRO MICROSYSTEMS, LLC MANCHESTER, NH | 67400/962 | PASDL, file of 2026-10-15 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.