Patents

US 11791438 B2: Heterostructure for an optoelectronic device

Granted
2023-10-17
Filed
2021-03-11 application 17198491
Type
Utility · 20 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

A heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can include a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.

Source: PVGPATDIS, file of 2026-04-10 (ipg231017.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
Sensor Electronic Technology, Inc. 362 patentsUS company or organizationColumbia, SCSENSOR ELECTRONIC TECHNOLOGY, INC. Federal lobbying client EXACT high confidence: identical full name and statePVGPATDIS, file of 2026-04-10

Inventors

InventorPlacePatentsPerson pageSource
Mikhail GaevskiColumbia, SC22PVGPATDIS, file of 2026-04-10
Alexander DobrinskyHouston, TX264PVGPATDIS, file of 2026-04-10
Maxim S. ShatalovFarmingville, NY165PVGPATDIS, file of 2026-04-10
Michael ShurVienna, VA346PVGPATDIS, file of 2026-04-10

CPC categories

SubclassCategoryFirst groupSource
H10HInorganic light-emitting semiconductor devices having potential barriersH10H20/0137PVGPATDIS, file of 2026-04-10
H01LSemiconductor devices not covered by class h10H01L21/6835PVGPATDIS, file of 2026-04-10
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light; devices using stimulated emission of electromagnetic radiation in wave ranges other than opticalH01S5/3209PVGPATDIS, file of 2026-04-10
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h10H10P72/74PVGPATDIS, file of 2026-04-10

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

No recorded assignments or security interests on file for this patent.

USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.