Patents
US 11519858 B2: Induced crosstalk circuit for improved sensor linearity
- Granted
- 2022-12-06
- Filed
- 2022-01-11 application 17572879
- Type
- Utility · 20 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
An optical sensor includes a detector having a printed circuit board (PCB) and an inductive loop. The printed circuit board (PCB) has a photodiode cathode pad with a photodiode. The inductive loop is arranged around at least part of the photodiode cathode pad, and configured to receive inductive loop inducing signaling, and provide inductive loop signaling around the at least part of the photodiode cathode pad to provide inductive on the PCB to reduce or substantially eliminate unwanted electrical interference in electrical photodiode signaling provided from the photodiode. The inductive loop includes a trace and at least one via. The trace has a route along a signal path from a transistor collector pin around an LED anode pad. The at least one via is placed between LED anode pads to route the trace on a top side of the PCB, and the trace is routed alongside, near and around the photodiode cathode pad back to the LED anode of the LED anode pad.
Source: PVGPATDIS, file of 2026-04-10 (ipg221206.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| YSI, INC. 24 patents | US company or organization | Yellow Springs, OH | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Kevin Flanagan | Yellow Springs, OH | 6 | PVGPATDIS, file of 2026-04-10 | |
| Steven M. Parmley | Centerville, OH | 2 | PVGPATDIS, file of 2026-04-10 | |
| Douglas J. Posey | Thornton, CO | 1 | PVGPATDIS, file of 2026-04-10 | |
| Michael Leiss | Versailles, OH | 1 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| G01N | Investigating or analysing materials by determining their chemical or physical properties | G01N21/64 | PVGPATDIS, file of 2026-04-10 |
| H05K | Printed circuits; casings or constructional details of electric apparatus; manufacture of assemblages of electrical components | H05K1/0216 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2022-08-12 | Assignment Assignment of assignor's interest | FLANAGAN, KEVIN R. signed 2022-03-14 LEISS, MICHAEL signed 2022-03-14 PARMLEY, STEVEN M. signed 2022-03-14 POSEY, DOUGLAS J. signed 2022-03-21 | YSI, INC. YELLOW SPRINGS, OH | 60793/964 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.