Patents
US 11069683 B2: Self restoring logic structures
- Granted
- 2021-07-20
- Filed
- 2019-09-26 application 16583820
- Type
- Utility · 8 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic. A SRL latch is formed of three NMOS and PMOS structures having a first latch with a first NMOS structure adjacent a first PMOS structure, a second latch with a second NMOS structure adjacent a second PMOS structure wherein the first and second NMOS structures are adjacent one another, and a third latch with a third NMOS structure adjacent a third PMOS structure wherein the second and third PMOS structures are adjacent one another, wherein the latch is adapted to have alternating logic with a state assignment of 010 and 101. A Single Event Upset Triple Modular Redundancy (TMR) tolerant circuit generates complementary output values 010 and 101 with layouts that are adjacent.
Source: PVGPATDIS, file of 2026-04-10 (ipg210720.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| ICs LLC 5 patents | US company or organization | McCall, ID | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Sterling Whitaker | Albuquerque, NM | 5 | PVGPATDIS, file of 2026-04-10 | |
| Gary Maki | Ponte Vedra, FL | 5 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| G06F | Electric digital data processing | G06F11/0751 | PVGPATDIS, file of 2026-04-10 |
| H10D | Inorganic electric semiconductor devices | H10D84/85 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2019-09-26 | Assignment Assignment of assignor's interest | MAKI, GARY signed 2019-09-25 WHITAKER, STERLING signed 2019-09-25 | ICS LLC MCCALL, ID | 50502/286 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.