Patents

US 10669627 B2: Multi-layer deposition system and process

Granted
2020-06-02
Filed
2017-08-30 application 15691593
Type
Utility · 12 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

A modular multilayer deposition system includes a plurality of modular deposition chambers, including at least one parylene deposition chamber and at least one ALD deposition chamber. The parylene deposition chamber is connected in series with the ALD deposition chamber. Substrates are automatically moved from within the parylene deposition chamber to within the ALD deposition chamber or from within the ALD deposition chamber to the parylene deposition chamber.

Source: PVGPATDIS, file of 2026-04-10 (ipg200602.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
HZO, Inc. 41 patentsUS company or organizationMorrisville, NCHZO, INC. Form D issuer EXACT high confidence: identical full name and statePVGPATDIS, file of 2026-04-10

Inventors

InventorPlacePatentsPerson pageSource
Yang YunDraper, UT9PVGPATDIS, file of 2026-04-10
Max SorensonHerriman, UT24PVGPATDIS, file of 2026-04-10
Chien-Lan HsuehDraper, UT19PVGPATDIS, file of 2026-04-10
Tining SuDraper, UT6PVGPATDIS, file of 2026-04-10
Jim DempsterReno, NV1PVGPATDIS, file of 2026-04-10
Alex AndersonDraper, UT3PVGPATDIS, file of 2026-04-10
Layton BakerDraper, UT4PVGPATDIS, file of 2026-04-10

CPC categories

SubclassCategoryFirst groupSource
C23CCoating metallic material; coating material with metallic material; surface treatment of metallic material by diffusion into the surface, by chemical conversion or substitution; coating by vacuum evaporation, by sputtering, by ion implantation or by chemical vapour deposition, in generalC23C16/45525PVGPATDIS, file of 2026-04-10
H01LSemiconductor devices not covered by class h10H01L21/67161PVGPATDIS, file of 2026-04-10
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h10H10P72/0452PVGPATDIS, file of 2026-04-10

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

RecordedWhatFromToReel/frameSource
2023-06-05Security interest Security interest
Security interest
HZO, INC. signed 2023-06-05
HZO HONG KONG LIMITED signed 2023-06-05
CATHAY BANK EL MONTE, CA63861/25PASDL, file of 2026-10-05
2019-10-21Assignment
Assignment of assignor's interest
DEMPSTER, JIM signed 2017-10-02
YUN, YANG signed 2017-10-03
ANDERSON, ALEX signed 2017-10-23
HSUEH, CHIEN-LAN signed 2017-11-01
SU, TINING signed 2017-12-17
SORENSEN, MAX signed 2017-12-21
HZO, INC. DRAPER, UT50777/863ECORSEXC, file of 2026-09-25
2019-09-17Assignment
Assignment of assignor's interest
BAKER, LAYTON signed 2019-08-19HZO, INC. DRAPER, UT50404/754ECORSEXC, file of 2026-09-25

Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.

USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.