Patents
US 10418270 B2: Wafer edge lift pin design for manufacturing a semiconductor device
- Granted
- 2019-09-17
- Filed
- 2017-12-07 application 15835184
- Type
- Utility · 16 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
A wafer edge lift pin of an apparatus for manufacturing a semiconductor device is described. The wafer edge lift pin includes an offset top section containing a notch portion to support and laterally confine the wafer. The notch portion horizontally sweeps away from the wafer along a radius so that rotation adjusts lateral confinement of the wafer. A base section below the top section has a diameter greater than a diameter of the top section across the notch portion to help strengthen the pin and to allow perpendicular mounting. A bottom section has a diameter that is smaller than the diameter of the base section and provides a boss feature to mount the lift pin. The apparatus includes a process chamber where the wafer is processed, a chuck assembly on which the wafer is loaded. At least three wafer edge lift pins move the wafer up and down.
Source: PVGPATDIS, file of 2026-04-10 (ipg190917.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| TEL FSI, INC. 34 patents | US company or organization | Chaska, MN | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Edward Hanzlik | Shorewood, MN | 7 | PVGPATDIS, file of 2026-04-10 | |
| Sean Moore | Maple Grove, MN | 11 | PVGPATDIS, file of 2026-04-10 | |
| Brian D. Hansen | Carver, MN | 2 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| H01L | Semiconductor devices not covered by class h10 | H01L21/68742 | PVGPATDIS, file of 2026-04-10 |
| H10P | Generic processes or apparatus for the manufacture or treatment of devices covered by class h10 | H10P72/7612 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2020-07-30 | Correction Conversion | TEL FSI, INC. signed 2019-12-31 | TEL MANUFACTURING AND ENGINEERING OF AMERICA, INC. CHASKA, MN | 53366/139 | PASDL, file of 2026-10-15 |
| 2018-10-04 | Assignment Assignment of assignor's interest | HANSEN, BRIAN D. signed 2018-10-02 HANZLIK, EDWARD D. signed 2018-10-02 MOORE, SEAN signed 2018-10-03 | TEL FSI, INC. CHASKA, MN | 47068/603 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.