Patents

US 10289341 B2: Operating parameter offsets in solid state memory devices

Granted
2019-05-14
Filed
2017-06-30 application 15640356
Type
Utility · 22 claims
Elsewhere
Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗

Abstract

Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.

Source: PVGPATDIS, file of 2026-04-10 (ipg190514.xml).

Assignees

AssigneeTypePlaceAlso on furp.orgSource
WESTERN DIGITAL TECHNOLOGIES, INC. 4,838 patentsUS company or organizationSan Jose, CAWESTERN DIGITAL TECHNOLOGIES INC. Federal lobbying client EXACT high confidence: identical full name and statePVGPATDIS, file of 2026-04-10

Inventors

InventorPlacePatentsPerson pageSource
Roi KirshenbaumHod HaSharon, IL4PVGPATDIS, file of 2026-04-10
Karin InbarRamat HaSharon, IL44PVGPATDIS, file of 2026-04-10
Idan GoldenbergRamat HaSharon, IL20PVGPATDIS, file of 2026-04-10
Nian Niles YangMountain View, CA87PVGPATDIS, file of 2026-04-10
Rami RomJerusalem, IL18PVGPATDIS, file of 2026-04-10
Alexander BazarskyNes Ziona, IL193PVGPATDIS, file of 2026-04-10
Ariel NavonBeit She'an, IL194PVGPATDIS, file of 2026-04-10
Philip ReusswigMountain View, CA24PVGPATDIS, file of 2026-04-10

CPC categories

SubclassCategoryFirst groupSource
G06FElectric digital data processingG06F3/0659PVGPATDIS, file of 2026-04-10
G06NComputing arrangements based on specific computational modelsG06N3/0499PVGPATDIS, file of 2026-04-10
G11CStatic storesG11C11/5642PVGPATDIS, file of 2026-04-10

Cooperative Patent Classification, as currently assigned (one row per subclass).

Assignments and security interests

RecordedWhatFromToReel/frameSource
2022-02-08Release of security interest
Release of security interest at reel 052915 frame 0566
JPMORGAN CHASE BANK, N.A. signed 2022-02-03WESTERN DIGITAL TECHNOLOGIES, INC. IRVINE, CA59127/1PASDL, file of 2026-10-15
2020-02-06Security interest Security interest
Security interest
WESTERN DIGITAL TECHNOLOGIES, INC. signed 2020-01-13JPMORGAN CHASE BANK, N.A., AS AGENT CHICAGO, IL52915/566PASDL, file of 2026-10-15
2017-10-12Assignment
Assignment of assignor's interest
YANG, NIAN NILES signed 2017-09-08
KIRSHENBAUM, ROI signed 2017-09-10
INBAR, KARIN signed 2017-09-11
REUSSWIG, PHILIP signed 2017-09-12
BAZARSKY, ALEXANDER signed 2017-09-14
ROM, RAMI signed 2017-09-17
GOLDENBERG, IDAN signed 2017-10-01
NAVON, ARIEL signed 2017-10-01
WESTERN DIGITAL TECHNOLOGIES, INC. IRVINE, CA43853/446ECORSEXC, file of 2026-09-25

Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.

USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.