Patents
US 10061571 B2: System and method for link time optimization
- Granted
- 2018-08-28
- Filed
- 2016-09-22 application 15273511
- Type
- Utility · 18 claims
- Elsewhere
- Google Patents ↗ · USPTO patent document ↗ · USPTO Patent Center record ↗
Abstract
A method for link time optimization comprises parsing, by a compiler, an intermediate representation file to determine what symbols are present in the intermediate representation file. The method comprises providing the symbols to a linker and creating, by the linker, a symbol use tree of all the symbols that are present in the intermediate representation file and other symbols in binary code received by the linker. The method further comprises discarding, by the linker, any received objects for which no use can be identified and all dependencies of the objects. The method includes providing, from the linker to the compiler, a preserve list of symbols, the preserve list comprising a list of symbols proven used by the objects and the intermediate representation files. The method comprises compiling the intermediate representation files and the objects based on the preserve list of symbols, and deleting, by the linker, any remaining unused objects.
Source: PVGPATDIS, file of 2026-04-10 (ipg180828.xml).
Assignees
| Assignee | Type | Place | Also on furp.org | Source |
|---|---|---|---|---|
| QUALCOMM Innovation Center, Inc. 93 patents | US company or organization | San Diego, CA | PVGPATDIS, file of 2026-04-10 |
Inventors
| Inventor | Place | Patents | Person page | Source |
|---|---|---|---|---|
| Sergei Larin | Austin, TX | 9 | PVGPATDIS, file of 2026-04-10 | |
| Shankar Kalpathi Easwaran | Austin, TX | 2 | PVGPATDIS, file of 2026-04-10 | |
| Hemant Kulkarni | Cedar Park, TX | 2 | PVGPATDIS, file of 2026-04-10 |
CPC categories
| Subclass | Category | First group | Source |
|---|---|---|---|
| G06F | Electric digital data processing | G06F8/4441 | PVGPATDIS, file of 2026-04-10 |
Cooperative Patent Classification, as currently assigned (one row per subclass).
Assignments and security interests
| Recorded | What | From | To | Reel/frame | Source |
|---|---|---|---|---|---|
| 2016-11-10 | Assignment Assignment of assignor's interest | KALPATHI EASWARAN, SHANKAR signed 2016-11-07 KULKARNI, HEMANT signed 2016-11-07 LARIN, SERGEI signed 2016-11-07 | QUALCOMM INNOVATION CENTER, INC. SAN DIEGO, CA | 40278/393 | ECORSEXC, file of 2026-09-25 |
Documents recorded with the USPTO Assignment Recordation Branch that list this patent. A security interest is a lender’s claim on the patent as collateral; a release ends it.
USPTO bulk data: PatentsView granted patents, disambiguated (PVGPATDIS) for patents, assignees, inventors, places and CPC categories; the USPTO Patent Assignment Dataset (ECORSEXC) for assignments and security interests. Patents filed in the last 20 years. No claims or full text. Links to other records are by name (and state): EXACT means the identical full name and state; FUZZY means a looser name match, with the confidence shown.